In response to the COVID-19 pandemic, governments have implemented a wide range of non-pharmaceutical interventions (NPIs). Monitoring and documenting government strategies during the COVID-19 crisis is crucial to understand the progression of the epidemic. Following a content analysis strategy of existing public information sources, we developed a specific hierarchical coding scheme for NPIs. We generated a comprehensive structured dataset of government interventions and their respective timelines of implementation. To improve transparency and motivate collaborative validation process, information sources are shared via an open library. We also provide codes that enable users to visualise the dataset. Standardization and structure of the dataset facilitate inter-country comparison and the assessment of the impacts of different NPI categories on the epidemic parameters, population health indicators, the economy, and human rights, among others. This dataset provides an in-depth insight of the government strategies and can be a valuable tool for developing relevant preparedness plans for pandemic. We intend to further develop and update this dataset until the end of December 2020. Measurement(s) time at medical intervention • medical intervention Technology Type(s) digital curation • content analysis strategy of existing information sources Factor Type(s) non-pharmaceutical intervention • date Sample Characteristic - Location global Measurement(s) time at medical intervention • medical intervention Technology Type(s) digital curation • content analysis strategy of existing information sources Factor Type(s) non-pharmaceutical intervention • date Sample Characteristic - Location global Machine-accessible metadata file describing the reported data: https://doi.org/10.6084/m9.figshare.12668792

An integrated quadruple voltage mixed quenching, and active resetting circuit (Q2RC) in a 150 nm CMOS process is presented in this paper. The Q2RC features an excess-bias voltage of 7.2 V, which is four times the 1.8 V supply voltage. The dead time can be adjusted from 7 ns to 29 ns, which corresponds to the count rate range from 34 Mcps to 142 Mcps. Post-layout simulation results for an external SPAD with an equivalent parasitic capacitance of 4 pF are reported. The achieved quenching time of the Q2RC is 1.75 ns, which results in 4.05 GV/s quenching slew rate, while the delay time is 1.1 ns, and the resetting time is 2.55 ns.

A fully integrated single-photon avalanche diode (SPAD) using a controllable fast mixed quenching and active resetting circuit (QRC) fabricated in a $0.35-\mu\mathrm{m}$ high-voltage CMOS process is presented in this paper. The QRC features a fast active quenching time of 0.52 ns and a minimum dead-time of 4.57 ns, which corresponds to a maximum count rate of 218 Mcps. To validate the quenching performance, the circuit was integrated together with a large-area SPAD having an active diameter of $90\ \mu\mathrm{m}$ with a capacitance of 150 fF. A pad for a pico-probe was integrated on the chip, leading to a total capacitive load of 275 fF in SPAD cathode's node during transient measurements.

A fully integrated single-photon avalanche diode (SPAD) using a high-voltage quenching circuit fabricated in a 0.35-μm CMOS process is proposed. The quenching circuit features a quenching voltage of 9.9 V, which is three times the nominal supply voltage to increase the photon detection probability (PDP). To prove the quenching performance, the circuit has been integrated together with a large-area SPAD having an active diameter of 90  μm. Experimental verification shows a maximum PDP of 67.8% at 9.9 V excess bias at a wavelength of 642 nm.

A voltage-controlled current amplifier/attenuator in a standard 0.35-<inline-formula> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> CMOS technology is presented. It is based on the resistive mirror method, using non-saturated MOSFETs. An open-loop design with no compensation capacitors provides a high stability and a small occupied chip area of 0.0126 mm². A current gain dynamic range of 513 (54.2 dB), a gain-bandwidth product of 1.78 GHz at the largest current gain of 35.9 dB, and a maximum power consumption of 250 <inline-formula> <tex-math notation="LaTeX">${\mu }\text{W}$ </tex-math></inline-formula> with a single supply voltage of 1.3 V are achieved. In addition, an AC current source has been designed, integrated on the same chip, and used as the input of the proposed voltage-controlled amplifier/attenuator.

A CMOS controllable constant-power source suitable for thermal-based sensor applications is presented in this paper. It is based on the resistive mirror method. The stability of the proposed controllable constant-power source is not dependent on either the load resistance or the generated power. A generated power dynamic range of 46.2 (33.3 dB), a load resistance dynamic range of 5 (14 dB), a voltage efficiency of 0.81, and a relative error of the generated power less than 2.3 %, with a single supply voltage of 10 V have been measured. The stability test has been carried out using the resistive load in a pulse mode operation confirming the predictions of the analysis performed. In addition, a figure of merit is introduced in order to improve the quality of the performance comparison among the state-of-the-art in the area of controllable constant-power sources.