An <italic>RC</italic> -to-digital converter (RCDC) for the measurement of the <italic>RC</italic> time constant of the resistor and capacitor connected in series is presented in this article. A simple RCDC design insensitive to parasitic capacitances is based on the single-slope integration. The output voltage of the integrator is linearly changed from half the value of the reference voltage to its final value. The <italic>RC</italic> time constant is equal to the duration of the single-slope integration and is independent of any other parameter. The proposed RCDC has been prototyped using discrete off-the-shelf components mounted on a printed circuit board, with a single supply voltage of 2.7 V. Measurements have been performed for 36 different combinations of the resistors and capacitors connected in series, where the measured time constant is in the range <inline-formula> <tex-math notation="LaTeX">$45.77 \mu \text{s} < $ </tex-math></inline-formula> <italic>RC</italic> < 2.32 ms, for three different reference voltages. The achieved relative error is smaller than 1.96% for the largest reference voltage used.

A current-mode interface (CMI) with mixed single/dual slope integration (MSDSI) for differential capacitive sensors (DCSs) is presented in this article. The proposed design is based on the integration of the reference current flowing through the capacitors of the DCS. The integration of the capacitor of a smaller capacitance is performed with a dual slope. Contrary, the integration on the capacitor of a larger capacitance is performed with only one slope. The normalized differential capacitance (NDC) defined as the difference-to-sum ratio of the DCS capacitances is proportional to the duration of only one time interval which is digitized using the counting method. There is no need for postprocessing in the proposed NDC-to-time-to-digital conversion. It has been prototyped using discrete off-the-shelf components mounted on a printed circuit board, with a single supply voltage of 3.3 V. The measured NDC is in the range $|\text {NDC}| < 0.612$ , with the constant sum of DCS capacitances of 970 pF. Achieved full-scale error is smaller than 0.3%, with a range of conversion speed from 1770 to 2755 NDC-to-time-to-digital conversions per second.

This paper presents a fully-integrated optical sensor with SPAD and mixed quenching/resetting circuit with sensing stage based on a tunable-threshold inverter optimized for the standard 0.35-µm CMOS technology. The presented quencher features a controllable detection threshold voltage and an adjustable total dead time. The quenching circuit 5QC achieves 16.5 V excess bias voltage (five times the supply voltage). The dead time ranges from 7.5 ns to 51.5 ns, which corresponds to a saturation count rate range from 19.4 Mcps to 133.3 Mcps. The quencher is optimized for SPADs with a capacitance ranging from 50 fF up to 400 fF. Using our published measured photon detection probability (PDP) results and extrapolating them, a peak PDP of 75.6% at 652 nm and a PDP of 39.2% at 854 nm is estimated for VEX = 16.5 V. To the authors' best knowledge, the presented PDP result has never been reached before for a fully-integrated SPAD sensor in standard CMOS technology.

Given the doping profiles available in different CMOS technologies, different single-photon avalanche diode (SPAD) structures could be designed. A good insight into the effect of various doping profiles on the electric field distribution within the device is crucial for optimizing the photodetection performance. In this paper, we present an experimental and simulation characterization of the photon detection probability (PDP) for two reach-through SPADs with different doping profiles, and study the effect of the electric field distribution on the PDP performance. We use a comprehensive model to evaluate the PDP up to an excess bias voltage of 13.2V. In addition, it is shown that the SPAD with a thicker high-field region, despite having the lower maximum value of the electric field, shows higher carrier avalanche triggering probabilities and, consequently, a higher PDP (67% at 13.2 V excess bias and a wavelength of 642 nm). The PDP at the wavelength of the absolute transmission maximum of the isolation and passivation stack at 665 nm is even 84% at 13.2 V excess bias. The presented results and discussions can offer a better insight to the designer to achieve higher PDP for other SPAD structures by optimizing the electric field profile using doping modifications.

An analog time of flight correlator designed in a 150 nm LFoundry CMOS process, capable of correlating photon pulses with an input clock for the use with single-photon avalanche diodes (SPADs) is presented. This correlator will allow highly sensitive and high precision indirect time of flight (iTOF) distance measurement with modulation frequencies up to 1 GHz and a distance resolution of 3 mm and 1.3 mm for a total measurement time of only $4\ \mu\mathrm{s}$ and $40\ \mu\mathrm{s}$, respectively. Additionally long integration times are possible, which guarantee operation with high background-to-signal-ratios (BSR). The small size and low power consumption of less than 1 mW allow the use of many correlators on a single chip. Two correlators and a quenching circuit are integrated on a chip with a size of $1.5 \times 1.3\ \text{mm}^{2}$. The size of a single correlator is $225 \times 143\ \mu\mathrm{m}^{2}$.

In this work a single photon avalanche diode (SPAD) based phase measurement circuit for distance measurements using continuously modulated light in a 150 nm CMOS technology is presented. An on-chip quadruple-voltage quenching circuit, allowing up to 7.2 V excess bias for external SPADs, generates pulses synchronous to the detection times of single photons. Circuit simulations show, that a precision of 0.54 mm can be achieved for distance measurements in low background light environments, in a measurement time of 200 μs. The efficiency of background light suppression can be improved by increasing the measurement time. Even a factor of 100:1 of background to measurement light should allow sub-cm precision given a sufficient measurement time. Correlation frequencies up to 1 GHz are possible. One correlator block has a size of 230×210 µm2 and the power consumption for each correlator is 391 µW.

This paper presents a fully-integrated optical sensor IC with SPAD, quenching/resetting circuit, and novel sensing stage based on a tunable-threshold inverter optimized for 0.35-μm high-voltage CMOS technology. The presented quencher features a controllable excess bias voltage and an adjustable total dead time. The excess bias voltage ranges from 10 V to a maximum of 22 V. The dead time ranges from 8 ns to 50 ns, which corresponds to a saturation count rate range from 20 Mcps to 125 Mcps. The quencher is optimized for the SPAD with a capacitance of 150 fF in the HV CMOS technology used. Using our recently published photon detection probability (PDP) model and fitting it to measured results up to a PDP of 68.8% at 9.9 V excess bias from our previous tapeout, a peak PDP of 90.1% (saturation PDP) at 650 nm for VEX=17.9 V is estimated and a PDP over 50% at 850 nm comes into reach for the same excess bias voltage. To the authors’ best knowledge, PDP saturation has never been reached before for an integrated SPAD.

In this letter we present a fast triple voltage quenching circuit (TVQC) with an integrated <inline-formula> <tex-math notation="LaTeX">$40~\mu \text{m}$ </tex-math></inline-formula> diameter single-photon avalanche diode (SPAD) in 0.35-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS. By pre-biasing the switching MOSFETs the reaction time of the TVQC is kept small, leading to a total quenching time of only 1.4 ns of which 0.61 ns are actively quenched. This short reaction time reduces the avalanche charge and therefore also the afterpulsing probability (APP). The dead time is adjustable from 7.9 ns to 200 ns, which allows further reducing the APP. Experimental verification shows an APP of 2.1% at a dead time of 30 ns. Using an integrated SPAD with a thick absorption zone allows achieving a photon detection probability (PDP) of 28.8% at 850 nm, while showing a peak PDP of 53.1% at 657 nm, both at 9.9 V excess bias.

An optical sensor IC in 0.35-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS is presented containing a single-photon avalanche diode (SPAD) and a fast quadruple-voltage quenching circuit (QVQC). The QVQC features a fast active quenching time of 0.93 ns, a total quenching time of 1.9 ns, and an adjustable total dead time (8.6–200 ns) to reduce the afterpulsing probability (APP). To verify the quenching performance, the circuit was integrated with a 40-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> diameter SPAD. Experiments show the reduction of afterpulsing by a low detection threshold and by fast quenching with a slew rate of 13.8 GV/s. Thus, an APP of 3.2% at 27-ns dead time, a peak photon detection probability (PDP) of 67.6% at 652 nm, and a PDP of 34.7% at 854 nm were measured at 13.2-V excess bias.