This paper presents a one solution for photovoltaic (PV) emulator. A main part of the developed PV emulator is buckconverter with recently proposed new I2 dual current mode control (I2 DCMC). The given simulation and experimental resultsdemonstrate excellent performances of the proposed PV emulator: matching between the characteristics obtained from the developedmathematical (simulation) model of the PV module and from the PV emulator, adaptability to the emulated changes in solar insolationand temperature, simple and efficient manipulation with PV module parameters and operating conditions, which is useful especially foreducation purposes, and fast dynamics.

In this paper method of implementation VS-PLL structure on FPGA circuit is described as well performances of proposed structure are presented. It was pointed out that special attention should be paid to the method of mapping VS-PLL structure from a continuous to a discrete domain, in order to does not volatile given performances. Also, it has been shown that MATLAB with all its tools can be used to perform these complex tasks.

Synchronisation block which is used as a part of photovoltaic (PV) inverters control structure has a key impact on connecting inverters with grid. One of the most important parameters in the point of connection PV inverter and grid is phase angle between grid voltage and inverter current. This angle determines the energy transfer between inverter and grid. Synchronisation alorithms have developed for very long time. At first, they were based on zero crossing grid voltage detection, while today complexed synchronisation algorithms implemented on high performance digital board have been used. One of these synchronisation structures  iz Phase Locked Loop – PLL. In this paper implementation of improved PLL structure is presented. This improved structure is special while it has posibillity of grid parameters estimation even if grid voltage has noise or DC offset. This DC offset from the grid in PLL structure usually entered via measurement and A/D conversion processor or may be generated due to temporary system faults. Appearance of DC offset in measured grid voltage on the one hand prevents any estimation process of grid parameters and on the other hand also degrades reference sine signal at the output of PLL structure in PV inverters. This improved structure is designed in digital form and implemented on FPGA digital board and experimental results of this implementation are presented. Obtained experimental results show that the proposed PLL structure successfully solves important issue such is presence of DC offset in measured grid voltage.

Phase-locked loops (PLLs) are doubtless the most popular synchronization technique in the power converters. Almost all proposed PLL structures known in literature are inherently nonlinear and can be linearized as second order linear time invariant system. Nonlinear nature of PLLs degrades their performances, and question arises if there exist an enhanced PLL structure that would have superior performances. In this paper we propose an three-phase nonlinear PLL structure based on sliding mode control theory and it is named variable structure PLL (VS-PLL). In order to implement this structure on an digital platform, fixed point mapping is performed and corresponding VHDL code is generated by MATLAB HDL coder. Excellent behaviors of continuous and discrete form VS-PLL structure in steady and transient states are confirmed by simulations.

This paper proposes an application of adaptive dual current mode control (ADCMC) on bidirectional bridgeless power factor correction (BBPFC) boost rectifier with unipolar switching. The given simulation results confirm the benefits of the proposed control strategy of the BBPFC converter, primarily regarding the maintaining of the sine waveform of the average inductor current.

This paper presents an implementation of adaptive dual current mode control (ADCMC) on non-inverting buck-boost converter. An experimental verification of the converter operation with the proposed ADCMC has been performed in steady state and during the step disturbances in the input voltage and the load resistance. The given experimental results confirm the effectiveness of the proposed control method.

Phase Locked Loop (PLL) is wide used for grid parameters estimation, as well for grid-converters synchronization. Key block at single-phase Synchronous Reference Frame PLL (SRF-PLL) structure is two-phase generator which is used for generation of two quadrature signals, which are necessary for SRF block. One of the issues that could appear during estimation of grid parameters is appearance of DC offset in measured grid voltage. In this paper is described second order generalized integrator (SOGI) which is capable to fully reject DC offset and noise which could appear in measured input grid voltage. This two-phase generator is named DC-SOGI. Analog DC-SOGI is made of two second order filters. While these structures are mostly digitally implemented, then it is interesting to analyze discretization method and sampling time impact on two-phase generator. Simulation results confirm given assumption.

In this paper, a new adaptive dual current mode control method (ADCMC) is presented, being a result of the modification of existing dual current mode control (DCMC) by introducing an adaptive current bandwidth. The ADCMC offers several important advantages over DCMC, such as no peak‐to‐average error in the inductor current, better transient response of current loop, and improved line regulation. A detailed analysis of the proposed ADCMC is performed for three types of DC–DC power electronics converters: buck, boost, and non‐inverting buck–boost converter. The performances of the ADCMC are tested with simulations and experiments. The obtained results confirm the analysis and validity of the proposed ADCMC method. Copyright © 2015 John Wiley & Sons, Ltd.

This paper proposes the usage of adaptive delay bank (ADB) based on cascaded delayed signal cancellation (CDSC) structure for selective elimination of the harmonics in the synchronous reference frame phase locked loop (SRF-PLL) structures. The ADB is inserted inside the SRF-PLL structure and it is frequency adaptive, which is the advantage over CDSC structures which are used in PLL as pre-filters, not being adaptive at all. Detailed mathematical analysis and simulation results confirmed suggested method for selective harmonic elimination in PLL.