Improved single-phase PLL structure with DC-SOGI block on FPGA board implementation
Synchronisation block which is used as a part of photovoltaic (PV) inverters control structure has a key impact on connecting inverters with grid. One of the most important parameters in the point of connection PV inverter and grid is phase angle between grid voltage and inverter current. This angle determines the energy transfer between inverter and grid. Synchronisation alorithms have developed for very long time. At first, they were based on zero crossing grid voltage detection, while today complexed synchronisation algorithms implemented on high performance digital board have been used. One of these synchronisation structures iz Phase Locked Loop – PLL. In this paper implementation of improved PLL structure is presented. This improved structure is special while it has posibillity of grid parameters estimation even if grid voltage has noise or DC offset. This DC offset from the grid in PLL structure usually entered via measurement and A/D conversion processor or may be generated due to temporary system faults. Appearance of DC offset in measured grid voltage on the one hand prevents any estimation process of grid parameters and on the other hand also degrades reference sine signal at the output of PLL structure in PV inverters. This improved structure is designed in digital form and implemented on FPGA digital board and experimental results of this implementation are presented. Obtained experimental results show that the proposed PLL structure successfully solves important issue such is presence of DC offset in measured grid voltage.