While modern FPGAs typically implement programmable logic using $\mathrm{4}-\mathrm{6}$-input LUTs, the Cologne Chip GateMate FPGA instead adopts a LUT-tree architecture, among several other distinctive features. We analyze its design trade-offs and support our findings with results from a targeted benchmark suite. LUT-trees prove less efficient for combinational logic than LUTs. Equivalent RTL designs (excluding DSPs) require ${1 0 - 3 0 \%}$ more programmable elements (CPEs) in GateMate than in comparable FPGAs. We observed a reduced logic-area efficiency, and the 1:1 flip-flop (FF) to logic ratio yields $30 \% \text{FF}$ under-utilization across diverse RTL designs. Comparative evaluation with a peer FPGA demonstrates that GateMate is suited for deeply pipelined applications with modest DSP and control requirements. Lack of timing-driven place and route, distributed RAM and DSP blocks limits usability for arithmetic-heavy, monolithic designs. We conclude that its dual-port block RAM and FF-dense fabric are strengths in particular application domains. Improved LUT-tree-optimized logic synthesis and constraint-driven place and route are required to increase its competitiveness.

Open-source RISC-V CPU architectures provide FPGA developers with fine-grained control over resource utilization and performance. This work presents a case study in throughput maximization and PPA (power, performance, area) optimization for a minimal RISC-V core on FPGA, with an emphasis on structured SystemVerilog design practices. We propose a short, single-cycle pipeline architecture targeting resource-constrained deployments and systematically compare its PPA characteristics against similar performance-class implementations. FPGA-specific optimizations, including tailored Register File and ALU configurations, are employed to improve critical path timing and overall throughput. The resulting design, eduBOS5, achieves a 2× increase in DMIPS/MHz while reducing LUT utilization by 24% compared to PicoRV32 on the Gowin LittleBee FPGA. PPA metric scaling over different FPGAs was addressed by porting the design to Xilinx and Lattice devices.

Motion tracking achieved via conventional video processing and machine vision algorithms is often hindered by challenges such as motion blur and the lack of distinctive visual features, particularly when tracking fast-moving objects. To address these limitations, active visual markers are often used. In this paper, we present the design and prototype implementation of an active marker that is compact, detachable, and self-powered, making it well-suited for real-world tracking applications. Furthermore, the marker is fully configurable through an accompanying software solution and an additional wireless communication controller via an infrared protocol. The applicability of the developed markers is demonstrated using both conventional RGB and event-based cameras, highlighting their versatility and robustness across diverse sensing modalities. Their tracking capabilities are validated in both single- and multi-object scenarios. Overall, the developed multi-functional markers provide a flexible and practical foundation for high-speed motion tracking under challenging visual conditions, paving the way for further research and advanced applications in related fields.

This paper proposes a mobile robot motion control and planning system for trajectory tracking and obstacle avoidance in a prior unknown robot environment. The proposed system has two-level control and planning architecture: the higher is used to generate a path, while the lower provides the control actions that drive the robot. The planning level represents a reactive planer which determines on-line way-points during the robot’s movement towards the target and allowing the robot to move autonomously through an environment without colliding with obstacles. The main objective of this algorithm is to reduce the number of obstacles that are taken into consideration when determining the intermediate target point (way-points) in the movement towards the target location. This proposed algorithm is based on the concept of calculating the intersection of the variable target circle and the robot perception circle (VTPC), as well as attractive and repulsive forces. The lower level includes a fuzzy logic controller that drives the robot along generated online trajectory. It compares the current position of the mobile robot with the desired position, generating the appropriate linear speeds for the robot’s wheels to reach the target point in the shortest possible time. A series of simulations demonstrate its effectiveness in generating and executing the paths in various unknown robot environments.

Timely and accurate defect detection is essential in the leather industry, as the quality of raw leather directly impacts both the usability and value of finished products. This paper provides a systematic overview of state-of-the-art solutions and proposes a novel approach for automated detection of leather surface defects using deep neural networks based on the Inception-V3 architecture. Five defect categories are introduced, focusing on their impact on leather quality. In addition, two deep neural network architectures were analyzed and implemented for defect detection and classification: a single-channel model and a multi-channel model with arbitration. The evaluation was carried out using a combination of a custom-developed dataset and publicly available datasets, assessed with standard performance metrics. Moreover, an image annotation tool was developed to facilitate precise defect labeling and the creation of variable-size datasets. Both models demonstrated promising results on the custom dataset, achieving accuracy rates exceeding 93%. The suggested methodology enhances the research domain of leather inspection automation by creating an openly accessible image dataset, performing a comparative analysis of detection models and creating software tools for data preparation. These contributions lay the foundation for further research in leather defect detection and potential industrial implementation.

This paper focuses on the design and implementation of a discrete digital PID (Proportional - Integral - Derivative) controller utilizing an FPGA (Field Programmable Gate Arrays) platform, which inherently supports parallel implementation of algorithms. Typically, cost-effective FPGA boards lacks peripherals, such as analog inputs and outputs, so they need to be added externally. The main hypothesis is that a DC motor system can be controlled with a low-cost variant of FPGA-based PID controllers. Therefore, an I2C (Inter-Integrated Circuit) based AD (Analog-to-digital) converter is added as input, while PWM (Pulse width modulation) based output signal is used as an output. The effectiveness of the designed regulator is demonstrated on an example of a DC (direct current) motor control. Additionally, for control and monitoring purposes, the FPGA is connected to the PC using the UART (Universal Asynchronous Receiver Transmitter) protocol. Experimental results indicate that the FPGA-based PID implementation offers solid performance.

This paper presents the development and implementation of a flexible industrial machine model for automated visual inspection, called ETFCam, designed to improve the learning outcomes of electrical engineering students in the field of machine vision and robotics. Unlike prefabricated didactic models, which are typically “closed” systems with a predefined set of experiments, custom didactic systems for teaching and training built from scratch tend to be more flexible and provide a deeper insight in engineering, machine design and planning, while being more cost-effective. The proposed system is based on a 3DOF stepper motor-based manipulator, a DC motor driven conveyor, a pneumatic actuated gripper and a machine vision system. The paper discusses several applications of such a system in an educational environment, with a special focus on machine vision applications. Due to the fact that the system is versatile, open, modular, and easy to upgrade, it has unlimited potential and possibilities for further development. In addition, it provides students with a perfect testbed for learning new engineering skills in many areas such as schematic drawing and understanding, PLC based control, sensing, and machine vision.

The paper presents an automated method for solving traditional single side 2D jigsaw puzzles, focusing solely on shape features. Termed as semi-apictorial puzzles, our approach utilizes pictorial content solely for image segmentation, not for puzzle matching. Through enhancements in background separation, corner extraction, and feature matching, our method simplifies and accelerates puzzle reconstruction. A key contribution is the introduction of an edge matching technique that employs approximate triangles to evaluate a possible match, which notably improves computational efficiency and reduces algorithm complexity. Experimental results demonstrate that the proposed method outperforms existing solutions, enabling the handling of a larger puzzles within a reasonable timeframe.

This paper explores the application of FPGA programmable structures in the field of digital image signal processing (ISP). FPGAs offer high flexibility, speed and parallelism, making them ideal for general digital signal processing (DSP), as well as specific ISP tasks. The paper utilizes standard ISP algorithms such as morphological operations, filtering and edge detection to compare practical implementations of FPGA and CPU-based compute engines. Through illustrative examples and empirical results, we demonstrate the distinct advantages of employing FPGA for these use-cases, and contrast them with traditional CPU approaches, clearly showing FPGA capacity to significantly accelerate execution. The challenges that arise from resource-limited IOT-class hardware configurations are highlighted in the paper, namely resource optimization, memory management and maximal frequency.

This paper introduces twisting sliding mode control method (TWSMC) to track 3D trajectories of a quadrotor unmanned aerial vehicle (UAV) exposed to bounded disturbances and perturbations. The key idea behind TWSMC is to introduce a nonlinear twisting term into the sliding surface design, which enables the system to switch between different sliding modes (SMs) smoothly, thereby reducing the chattering phenomenon and improving control performance. Moreover, a high-gain adaptation (HGA) algorithm is adopted in the TWSMC scheme to additionally attenuate the chattering effect, where the switching control gain increases during the convergent phase and decreases in the sliding phase. Through the comprehensive simulation study, it is shown that the proposed approach exhibits improved robustness and performance in tracking a reference under disturbances and perturbations.