Channel coding is a common technique used to reduce bit-error rate (BER) in a communication channel. In cases where a certain block code is used, there is a known procedure for determining a residual BER (bit-error rate after encoding and decoding). Analysis in opposite direction should determine a block code parameters for optimising system performance in terms of reliability and throughput. This paper proposes an iterative method for addressed problem by introducing some auxiliary function, whose inverse can be written in closed form. We demonstrate the usage of proposed method in determining parameters of suitable binary BCH code to improve error probability during the transmission of BPSK signal over Rayleigh fading channel. The correctness of analytically obtained results are validated by simulation results.

The software-defined networking (SDN) is an articulation of the idea of increasing the network programmability with the aim of solving the problems identified in earlier research, regarding the complex and the time-consuming process of the protocol and interface standardization. An analysis of research in the field of SDN, presented through various review and survey papers, has shown that previous research was not sufficiently focused on flexibility and programmability of the data plane in SDN. Therefore, the goal of this paper is to improve the flexibility of the data plane in SDN by increasing the programmability level of the packet-switching node. To achieve the set goal, it was necessary to choose an appropriate metric for evaluation of flexibility and programmability of the data plane. Since there is no common position on the choice of metrics, a novel metric based on qualitative criteria is proposed in this paper. An existing data plane architectures in SDN are observed through the proposed metric. In the end, a novel data plane architecture, with improved flexibility from the aspect of the qualitative metric, is proposed.

Software-defined networking (SDN) has attracted the attention of the research community in recent years, as evidenced by a large number of survey and review papers. The architecture of SDN clearly recognizes three planes: application, control, and data planes. The application plane executes network applications, the control plane regulates the rules for the entire network based on the requests generated by network applications, and based on the set rules, the controller configures the switches in the data plane. The role of the switch in the data plane is to simply forward packets based on the instructions given by the controller. By analyzing the SDN-related research papers, it is observed that research, from the very beginning, is insufficiently focused on the data plane. Therefore, this paper gives a comprehensive overview of the data plane survey with a particular emphasis on the problem of programmability and flexibility. The first part of the survey is dedicated to the evaluation of actual data plane architectures through several definitions and aspects of data plane flexibility and programmability. Then, an overview of the SDN-related research was presented with the aim of identifying the key factors influencing the gradual deviation from the original data plane architectures given with ForCES and OpenFlow specifications. In this paper, we used the term data plane evolution for this deviation. By establishing a correlation between the treated problem and the problem-solving approaches, the limitations of ForCES and OpenFlow data plane architectures were identified. Based on the identified limitations, a generalization of approaches to addressing the problem of data plane flexibility and programmability has been made. By examining the generalized approaches, open issues have been identified, establishing the grounds for future research directions proposal.

In order to ensure the required wireless communication system performances, it is necessary to have an efficient communication channel model, which is capable of considering all channel degradation factors fairly. In this paper, a unified hollow-disk geometrically based stochastic channel model is derived. This model assumes that the scatterers are distributed in a hollow-disk area around a mobile station. Namely, the scatterer distribution is derived as a projection of $\boldsymbol{d}$-dimensional uniformly distributed scatterers into two-dimensional space. According to this generalization, derived model is capable of obtaining uniform circular, uniform ring, uniform hollow-disk, and unified disk scattering model as special cases, as well as modeling a whole new group of hollow-disk models. Under an assumption of single bounce scattering and omnidirectional antennas at transmitter and receiver, joint probability density function (PDF) of angle-of-departure and angle-of-arrival, as well as the joint PDF of time-of-arrival and angle-of-arrival are derived. Subsequently, the corresponding marginal PDFs are provided in a closed form. Thus, derived PDFs are suitable for any position of the base station, (base station placed inside or outside of scattering region). The proposed model is validated by several measured channels. The curve fitting results shown the high flexibility of the proposed model and outperforming results compared with several other geometric scattering models.

Software-Defined Networks (SDN) simplify tasks performed by the network switches and centralize the network management by clearly separating networking processes into an application, control, and data plane. An OpenFlow, the flagship of SDN implementation, has reduced the innovation of such networks by diminishing switching tasks to the simple lookup of packet flow tables. A novel hybrid architecture of a deeply programmable packet-switching node (DPPSN), based on field-programmable gate array (FPGA) and central processing unit (CPU) technologies, is proposed, with the aim of overcoming OpenFlow’s limitations regarding the ability to implement new protocols and advanced packet processing functionalities. It has been demonstrated, through the implementation and experimental evaluation of the DPPSN, that it is justified to use hybrid FPGA/CPU architecture for this purpose.