Quantifying the thermal boundary conductance of 2D-substrate interfaces
Two-dimensional (2D) materials have tremendous potential for next-generation nano- and opto-electronics [1], [2]. However, heat dissipation and its removal from hot spots in the monolayer remains a critical concern to the design of 2D-based devices [2], [3]. Thermal currents flowing in a atomic layer can either dissipate through source/drain contacts, as in a transistor configuration, or through a supporting substrate via van der Waals (vdW) coupling to it. When a 2D mateiral is supported by a substrate, the interfacial area formed between it and the substrate is often far larger than the lateral source/drain contact area. Thus, it is suspected that the majority of waste heat is removed across the 2D-substrate interface and then via the substrate. Therefore, it is imperative that the thermal boundary conductance (TBC) between the 2D layer and substrate be well characterized for reliable 2D device performance. Herein we tackle the question of selecting the best substrate for each 2D material from the point of view of heat dissipation.