A Lightweight UART-Based In-System Debugging Interface for RISC-V SoC on FPGA
This paper presents a novel UART-based debugging interface for resource-constrained RISC-V soft-core implementations on FPGAs. Unlike traditional JTAG-based approaches that require dedicated hardware and tools, our design leverages the ubiquitous UART peripheral to provide comprehensive debug capabilities through a dual-mode architecture. The interface operates in standard ASCII mode for command-line interaction and switches to a binary protocol for advanced operations including bulk instruction memory programming (IMPR), singleinstruction hot-patching (IMWR), and direct memory/CSR bus read/write operations (BUSR/BUSW). A key innovation is the bus mastering mechanism that enables real-time memory inspection and modification without permanent CPU halting, facilitating live debugging and in-field firmware updates. The FSM-based protocol incorporates checksum verification and timeout recovery for robust operation. Implemented on an 80 MHz RISC-V based SoC for WireGuard VPN acceleration, the interface consumes less than 2% additional FPGA resources while providing functionality comparable to more complex debug modules. Experimental results demonstrate successful hot-patching of running programs, sub-second firmware updates, and effective production diagnostics without requiring specialized JTAG hardware or tools.