This paper proposes an ac fault ride-through (FRT) method for high-voltage dc (HVDC) transmission systems that serve as an interconnector between the onshore ac grid and an islanded offshore ac grid. In conventional HVDC systems for offshore wind farms FRT is realized by consuming excess power with braking resistors. However, the same method cannot be applied if the offshore ac grid includes not only wind farms but also various loads, which are being considered for integration into multipurpose interconnectors or energy islands. In this article, a novel FRT method based on voltage control for HVDC interconnectors operating with bidirectional power flow is proposed. The proposed method curtails the ac voltage formed by the offshore converter according to the converter’s dc current and voltage. The effectiveness of the proposed FRT method is established through experiments on a mini model.

This paper discusses a low-voltage ride-through (LVRT) method for high-voltage direct current (HVDC) transmission systems that serve as an interconnector between the main onshore ac grid and an islanded offshore ac load. When a line-to-ground fault occurs in the onshore ac grid, a voltage sag will be applied to the HVDC transmission system. This sag will cause fluctuations of the dc voltage, which will cause a shutdown of the entire HVDC system. The proposed LVRT method stabilizes the dc voltage of the HVDC transmission line by reducing the amplitude of the voltage of the offshore ac grid, which is kept constant during normal operation. The proposed method allows the HVDC system to remain connected during voltage sags in the onshore ac grid and enables faster transmission recovery after fault clearance. The validity of the proposed LVRT method is verified by simulations.

This article presents a novel circuit configuration of a high-voltage direct current circuit breaker (HVdcCB) test bench that is based on a modified H-bridge modular multilevel cascaded converter (MMCC). The modified MMCC is composed of fewer H-bridge cells, and it can be reconfigured during operation to allow the proposed test bench to output large current or high voltage for the current breaking and dielectric withstand tests. Although simultaneous output of large current and high voltage is not possible, the maximum transient interrupt voltage (TIV) withstand test can be performed with reduced ratings. The controllable output allows generation of complex waveforms to simulate a wide range of fault conditions. Furthermore, the modified MMCC has some inherent safety features that can reduce the need for additional protective equipment in case of operational failure of the HVdcCB. In contrast, the conventional charged capacitor and inductor-based designs cannot generate arbitrary waveforms, are only suitable for current breaking tests, and require additional circuits to generate initial conditions for the HVdcCB. AC short-circuit generator-based designs offer one degree of freedom for control of the output waveforms and can sustain the maximum TIV withstand test. However, the ac output is unsuitable for the dielectric withstand test, and additional circuits are required to provide initial conditions for the HVdcCB. The proposed test bench circuit configuration is verified using a downscaled experimental test bench that consists of a total of nine H-bridge cells with an equivalent switching frequency of 92.5 kHz.

High-voltage direct current (HVDC) circuit breaker development and deployment strongly depend on the testing process, which ensures that the HVDC circuit breakers will satisfy design requirements. This article presents an HVDC circuit breaker test bench circuit configuration that can provide controllable large output currents to simulate different fault conditions for the current breaking test and high output voltage for the dielectric withstand test. The current breaking test circuit is based on multiple cascaded power converters connected in parallel to provide the necessary output current capability. Each cascaded power converter is composed of multiple cells that are operated by a phase-shifted pulsewidth-modulated signal for greater controllability and higher quality of the output waveform. The dielectric withstand test circuit is a simple high-voltage source with a low power rating that can also be used to charge the test bench and the internal circuitry of the circuit breaker that is to be tested. The proposed test bench ensures that fault conditions can be replicated accurately and offers greater flexibility by being able to test mechanical, semiconductor-based, or hybrid HVDC circuit breakers with different current and voltage ratings on the same hardware without any changes. The idea and the operating principle of the proposed test bench are verified experimentally on a downscaled system that consists of three cascaded power converters connected in parallel with three cells per cascaded power converter and with a total equivalent switching frequency of 92.5 kHz.

This paper proposes a novel circuit configuration for a high-voltage direct-current circuit breaker (HVDCCB) test bench that differs significantly from conventional test benches. The proposed test bench consists of a modular multilevel cascaded converter (MMCC) that is based on H-bridge cells, an output inductor, and an auxiliary capacitor bank. The proposed test bench is capable of generating controllable output currents up to several kiloamperes and output voltages up to several hundred kilovolts because each MMCC cell is operated by phase-shifted pulse-width-modulated (PSPWM) signals. Consequently, the proposed test bench can simulate a wide range of fault conditions within hardware limitations to test different HVDCCB types with various current and voltage ratings. The flexibility of the proposed test bench is complemented by a longer service lifetime with inherent circuit protection in the case of operational failure of the HVDCCB. The concept of the proposed test bench is verified experimentally on a downscaled test bench that consists of nine H-bridge cells and operates at an equivalent switching frequency of $\mathrm {92.5 kHz }$ .

This paper discusses the design and analysis of a modified test bench for high-voltage direct-current (HVDC) circuit breakers which consists of a power converter based on multiple cascaded H-bridge cells, a small-sized inductor, and an auxiliary capacitor bank. It is capable of producing output voltages up to several hundred kilovolts depending on the auxiliary capacitor bank while allowing for high current controllability via the power converter which is driven by phase-shifted pulse-width-modulated (PSPWM) signals. Consequently, the test bench can generate a wide range of controllable current waveforms and high current gradients, within hardware limitations, to simulate a wide range of fault conditions. The flexibility of the proposed design is complemented by higher reliability and longer lifetime. The concept of the test bench was verified by experiments using a down-scaled model based on nine cascaded H-bridge cells with an equivalent switching frequency of 92.5 kHz.

Growing popularity of recreational skiing and snowboarding in this region has directed this corpus-based study towards getting an insight into standardization requirements of the ski register in Serbian within the framework of today’s angloglobalized world of sport. The corpus consists of 292 ski terms in English and Serbian. After a brief overview of the creation of ski terms, the paper deals with a contrastive analysis of the corpus from the aspect of adaptation of English terms into the system of Serbian at the level of form, i.e. respelling and at the level of content, i.e. translation. Guided by the results of this analysis, the following sections deal with the requirements related to the standardization of ski terms in Serbian.