This paper presents the experimental research on the influence of clock synchronisation in a multi-transceiver radar system in terms of phase noise and stability of the clock source. The work involves an implementation of a clock distribution method and discusses the experimental results. The TIGER-3 radar is being developed as an “all digital” radar with 20 integrated digital transceivers, each operating at 2.4kW of nominal power. Accurate coordination of all 20 transceivers is essential for generation of transmit signals, collection and merging of receive data to form a standard SuperDARN data set. Therefore, the system clock frequency must be highly stable and be tightly synchronised. In order to achieve this, a clock synchronisation method to coordinate the operation of entire system using a highly stable, accurate common clock source distributed to the transceivers is proposed. To improve noise immunity, differential signals are used. To further enhance the electromagnetic interference (EMI) immunity of the clock system, magnetic circuitry is employed. Moreover, the FPGA clocking features including Digital Clock Managers (DCMs) and Phase-Locked Loops (PLLs) available on the Xilinx Virtex-5 devices are used to correct and recover the received clock. Test results show that the clock system has excellent noise immunity allowing the radar system to perform at its full power.

This paper presents a novel FPGA based method to implement a repeated squared-and-multiply algorithm in polynomial rings. The repeated square-and-multiply algorithm for exponentiation is discussed and constructed for a general function f(x). From that, an algorithm to apply for f(x)=xn+1 is also constructed and described in this paper. Simulations and implementation results using an FPGA are provided and discussed.

This paper describes a quad-channel Field Programmable Gate Array (FPGA) controlled Electrical Impedance Tomography (EIT) modular device and the calibration techniques used to characterize the system. Each module consists of four independently sampled analog channels and a single FPGA. The system is modular and the number of total channels is scalable to the individual intended application. Each module stores its own calibration coefficients for phase and voltage, enabling the user to acquire precise real and imaginary components of the impedance at various excitation frequencies.

The TIGER-3 radar is being developed as an “all digital” radar with 20 integrated digital transceivers, each connected to a separate antenna. Accurate coordination of all 20 transceivers is essential for both generation of transmit signals and collection and merging of receive data to form a standard Su-perDARN data set. This paper proposes a clock synchronisation method to coordinate the operation of the entire system using Field Programmable Gate Array (FPGA) technology. The method is a co-operation between hardware and software to achieve the necessary clock quality and synchronisation requirements. It is extremely important that the clock signals are kept aligned in time within specified bounds. To achieve this a 125Mhz common master clock is sent from a clock controller to a clock buffer, which then distributes the signals to the transceivers. In turn, each transceiver sends back a clock signal which is a buffered version of the common clock in the same bundle. In order to synchronise clocks on the transceivers, phase delays of round-trip clock paths are measured on the clock controller board with the accuracy of 31.25ps. The measurement is performed by shifting the common clock phase at a resolution of 1/256 of the clock period until the return clock and the common clock are in phase. Once the measurement cycle is complete, each transceiver adjusts the phase of its clock as directed by the clock controller. Experimental results show that the phase noise of the transmit signal generated from the synchronised clocks at transceivers is less than −100 dBc/Hz, while the SNR of the transmit signal is ≈ 90 dB for the entire 8–20 MHz range.