Over the recent decade, many different concepts of new emerging memories have been proposed. Examples of such include ferroelectric random access memories (FeRAMs), phase-change RAMs (PRAMs), resistive RAMs (RRAMs), magnetic RAMs (MRAMs), nano-crystal floating-gate flash memories, among others. The ultimate goal for any of these memories is to overcome the limitations of dynamic random access memories (DRAM) and flash memories. Non-volatile memories exploiting resistive switching – resistive RAM (RRAM) devices – offer the possibility of low programming energy per bit, rapid switching, and very high levels of integration – potentially in 3D. Resistive switching in a silicon-based material offers a compelling alternative to existing metal oxide-based devices, both in terms of ease of fabrication, but also in enhanced device performance. In this thesis I demonstrate a redox-based resistive switch exploiting the formation of conductive filaments in a bulk silicon-rich silicon oxide. My devices exhibit multi-level switching and analogue modulation of resistance as well as standard two-level switching. I demonstrate different operational modes (bipolar and unipolar switching modes) that make it possible to dynamically adjust device properties, in particular two highly desirable properties: non-linearity and self-rectification. Scanning tunnelling microscopy (STM), atomic force microscopy (AFM), and conductive atomic force microscopy (C-AFM) measurements provide a more detailed insight into both the location and the dimensions of the conductive filaments. I discuss aspects of conduction and switching mechanisms and we propose a physical model of resistive switching. I demonstrate room temperature quantisation of conductance in silicon oxide resistive switches, implying ballistic transport of electrons through a quantum constriction, associated with an individual silicon filament in the SiOx bulk. I develop a stochastic method to simulate microscopic formation and rupture of conductive filaments inside an oxide matrix. I use the model to discuss switching properties – endurance and switching uniformity.

The rapid development of computing technology is reflected in the fact that industry has consistently doubled the number of transistors per unit area on a semiconductor wafer every two years. Essentially the basic business model of the semiconductor industry, processor and memory technology has so far continued to roughly fulfil this doubling convention, despite technological barriers and fluctuating economic conditions. Many other aspects of computing technology have followed similar exponential laws, including hard drive space and internet connection speeds. However, the expiry of such rapid development has been forecast on multiple occasions as technological hurdles become increasingly more challenging.

A simple analytic model for the electron transport through filamentary-type structures in Si-rich silica (SiOx)-based resistive switches is proposed. The model is based on a mesoscopic description and is able to account for the linear and nonlinear components of conductance that arise from both fully and partially formed conductive channels spanning the dielectric film. Channels are represented by arrays of identical scatterers whose number and quantum transmission properties determine the current magnitude in the low and high resistance states. We show that the proposed model not only reproduces the experimental current-voltage (I-V) characteristics but also the normalized differential conductance (dln(I)/dln(V)-V) curves of devices under test.

We report a study of resistive switching in a silicon-based memristor/resistive RAM (RRAM) device in which the active layer is silicon-rich silica. The resistive switching phenomenon is an intrinsic property of the silicon-rich oxide layer and does not depend on the diffusion of metallic ions to form conductive paths. Both unipolar and bipolar programming is demonstrated. Switching exhibits the pinched hysteresis I/V loop characteristic of RRAM/memristive systems, and on/off resistance ratios of 104:1 or higher can be easily achieved. Scanning Tunnelling Microscopy suggests that switchable conductive pathways are 10nm in diameter or smaller. © 2012 Materials Research Society.