Resistive random-access memories, also known as memristors, whose resistance can be modulated by the electrically driven formation and disruption of conductive filaments within an insulator, are promising candidates for neuromorphic applications due to their scalability, low-power operation and diverse functional behaviors. However, understanding the dynamics of individual filaments, and the surrounding material, is challenging, owing to the typically very large cross-sectional areas of test devices relative to the nanometer scale of individual filaments. In the present work, conductive atomic force microscopy is used to study the evolution of conductivity at the nanoscale in a fully CMOS-compatible silicon suboxide thin film. Distinct filamentary plasticity and background conductivity enhancement are reported, suggesting that device behavior might be best described by composite core (filament) and shell (background conductivity) dynamics. Furthermore, constant current measurements demonstrate an interplay between filament formation and rupture, resulting in current-controlled voltage spiking in nanoscale regions, with an estimated optimal energy consumption of 25 attojoules per spike. This is very promising for extremely low-power neuromorphic computation and suggests that the dynamic behavior observed in larger devices should persist and improve as dimensions are scaled down.

Recent years have seen a rapid rise of artificial neural networks being employed in a number of cognitive tasks. The ever‐increasing computing requirements of these structures have contributed to a desire for novel technologies and paradigms, including memristor‐based hardware accelerators. Solutions based on memristive crossbars and analog data processing promise to improve the overall energy efficiency. However, memristor nonidealities can lead to the degradation of neural network accuracy, while the attempts to mitigate these negative effects often introduce design trade‐offs, such as those between power and reliability. In this work, authors design nonideality‐aware training of memristor‐based neural networks capable of dealing with the most common device nonidealities. The feasibility of using high‐resistance devices that exhibit high I‐V nonlinearity is demonstrated—by analyzing experimental data and employing nonideality‐aware training, it is estimated that the energy efficiency of memristive vector‐matrix multipliers is improved by almost three orders of magnitude (0.715 TOPs−1W−1 to 381 TOPs−1W−1) while maintaining similar accuracy. It is shown that associating the parameters of neural networks with individual memristors allows to bias these devices toward less conductive states through regularization of the corresponding optimization problem, while modifying the validation procedure leads to more reliable estimates of performance. The authors demonstrate the universality and robustness of this approach when dealing with a wide range of nonidealities.

Columnar microstructures are critical for obtaining good resistance switching properties in SiO x resistive random access memory (ReRAM) devices. In this work, the formation and structure of columnar boundaries are studied in sputtered SiO x layers. Using TEM measurements, we analyze SiO x layers in Me–SiO x –Mo heterostructures, where Me = Ti or Au/Ti. We show that the SiO x layers are templated by the Mo surface roughness, leading to the formation of columnar boundaries protruding from troughs at the SiO x /Mo interface. Electron energy-loss spectroscopy measurements show that these boundaries are best characterized as voids, which in turn facilitate Ti, Mo, and Au incorporation from the electrodes into SiO x . Density functional theory calculations of a simple model of the SiO 2 grain boundary and column boundary show that O interstitials preferentially reside at the boundaries rather than in the SiO 2 bulk. The results elucidate the nature of the SiO x microstructure and the complex interactions between the metal electrodes and the switching oxide, each of which is critically important for further materials engineering and the optimization of ReRAM devices.

Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >106 cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products.

The limited sensitivity of existing analysis techniques at the nanometer scale makes it challenging to systematically examine the complex interactions in redox-based resistive random access memory (ReRAM) devices. To test models of oxygen movement in ReRAM devices beyond what has previously been possible, we present a new nanoscale analysis method. Harnessing the power of secondary ion mass spectrometry, the most sensitive surface analysis technique, for the first time, we observe the movement of 16 O across electrically biased SiO x ReRAM stacks. We can therefore measure bulk concentration changes in a continuous profile with unprecedented sensitivity. This reveals the nanoscale details of the reversible field-driven exchange of oxygen across the ReRAM stack. Both the reservoir-like behavior of a Mo electrode and the injection of oxygen into the surface of SiO x from the ambient are observed within one profile. The injection of oxygen is controllable through changing the porosity of the SiO x layer. Modeling of the electric fields in the ReRAM stacks is carried out which, for the first time, uses real measurements of both the interface roughness and electrode porosity. This supports our findings helping to explain how and where oxygen from ambient moisture enters devices during operation.

Resistive random-access memories, also known as memristors, whose resistance can be modulated by the electrically driven formation and disruption of conductive filaments within an insulator, are promising candidates for neuromorphic applications due to their scalability, low-power operation and diverse functional behaviours. However, understanding the dynamics of individual filaments, and the surrounding material, is challenging, owing to the typically very large cross-sectional areas of test devices relative to the nanometre scale of individual filaments. In the present work, conductive atomic force microscopy is used to study the evolution of conductivity at the nanoscale in a fully CMOS-compatible silicon suboxide thin film. Distinct filamentary plasticity and background conductivity enhancement are reported, suggesting that device behaviour might be best described by composite core (filament) and shell (background conductivity) dynamics. Furthermore, constant current measurements demonstrate an interplay between filament formation and rupture, resulting in current-controlled voltage spiking in nanoscale regions, with an estimated optimal energy consumption of 25 attojoules per spike. This is very promising for extremely low-power neuromorphic computation and suggests that the dynamic behaviour observed in larger devices should persist and improve as dimensions are scaled down.

Machine learning, particularly in the form of deep learning (DL), has driven most of the recent fundamental developments in artificial intelligence (AI). DL is based on computational models that are, to a certain extent, bio‐inspired, as they rely on networks of connected simple computing units operating in parallel. The success of DL is supported by three factors: availability of vast amounts of data, continuous growth in computing power, and algorithmic innovations. The approaching demise of Moore's law, and the consequent expected modest improvements in computing power that can be achieved by scaling, raises the question of whether the progress will be slowed or halted due to hardware limitations. This article reviews the case for a novel beyond‐complementary metal–oxide–semiconductor (CMOS) technology—memristors—as a potential solution for the implementation of power‐efficient in‐memory computing, DL accelerators, and spiking neural networks. Central themes are the reliance on non‐von‐Neumann computing architectures and the need for developing tailored learning and inference algorithms. To argue that lessons from biology can be useful in providing directions for further progress in AI, an example‐based reservoir computing is briefly discussed. At the end, speculation is given on the “big picture” view of future neuromorphic and brain‐inspired computing systems.

The ever‐increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes inspiration from the highly parallel, low‐power, high‐speed, and noise‐tolerant computing capabilities of the brain, may provide such a shift. Many researchers from across academia and industry have been studying materials, devices, circuits, and systems, to implement some of the functions of networks of neurons and synapses to develop neuromorphic computing platforms. These platforms are being designed using various hardware technologies, including the well‐established complementary metal‐oxide semiconductor (CMOS), and emerging memristive technologies such as SiOx‐based memristors. Herein, recent progress in CMOS, SiOx‐based memristive, and mixed CMOS‐memristive hardware for neuromorphic systems is highlighted. New and published results from various devices are provided that are developed to replicate selected functions of neurons, synapses, and simple spiking networks. It is shown that the CMOS and memristive devices are assembled in different neuromorphic learning platforms to perform simple cognitive tasks such as classification of spike rate‐based patterns or handwritten digits. Herein, it is envisioned that what is demonstrated is useful to the unconventional computing research community by providing insights into advances in neuromorphic hardware technologies.

Memristors have many uses in machine learning and neuromorphic hardware. From memory elements in dot product engines to replicating both synapse and neuron wall behaviors, the memristor has proved a versatile component. Here we demonstrate an analog mode of operation observed in our silicon oxide memristors and apply this to the problem of edge detection. We demonstrate how a potential divider exploiting this analog behavior can prove a scalable solution to edge detection. We confirm its behavior experimentally and simulate its performance on a standard testbench. We show good performance comparable to existing memristor based work with a benchmark score of 0.465 on the BSDS500 dataset, while simultaneously maintaining a lower component count.

been through the copyediting, typesetting, pagination and proofreading process, which may lead to differences between this version and the Version of Record. Please cite this article as doi: 10.1002/aisy.201900189. This article is protected by copyright. All rights reserved CMOS and Memristive Hardware for Neuromorphic Computing Mostafa Rahimi Azghadi, Ying-Chen Chen, Jason K. Eshraghian, Jia Chen, Chih-Yang Lin, Amirali Amirsoleimani, Adnan Mehonic, Anthony J Kenyon, Burt Fowler, Jack C Lee, Yao-Feng Chang College of Science and Engineering, James Cook University, Townsville, QLD 4811, Australia Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78712, United States Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MI 48109-2122, United States Huazhong University of Science and Technology, Wuhan, Hubei, 430074, China Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada Department of Electronic and Electrical Engineering, University College London, Torrington Place, London, United Kingdom mostafa.rahimiazghadi@jcu.edu.au, yfchang@utexas.edu ABSTRACT The ever-increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes A cc ep te d A rti cl e

been through the copyediting, typesetting, pagination and proofreading process, which may lead to differences between this version and the Version of Record. Please cite this article as doi: 10.1002/aisy.201900189. This article is protected by copyright. All rights reserved CMOS and Memristive Hardware for Neuromorphic Computing Mostafa Rahimi Azghadi, Ying-Chen Chen, Jason K. Eshraghian, Jia Chen, Chih-Yang Lin, Amirali Amirsoleimani, Adnan Mehonic, Anthony J Kenyon, Burt Fowler, Jack C Lee, Yao-Feng Chang College of Science and Engineering, James Cook University, Townsville, QLD 4811, Australia Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78712, United States Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, MI 48109-2122, United States Huazhong University of Science and Technology, Wuhan, Hubei, 430074, China Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada Department of Electronic and Electrical Engineering, University College London, Torrington Place, London, United Kingdom mostafa.rahimiazghadi@jcu.edu.au, yfchang@utexas.edu ABSTRACT The ever-increasing processing power demands of digital computers cannot continue to be fulfilled indefinitely unless there is a paradigm shift in computing. Neuromorphic computing, which takes A cc ep te d A rti cl e