In this work, a new IDDQ built-in self-test (BIST) solution is proposed to provide accurate on-chip current measurements for phase-locked loops (PLLs) found in deep-submicron system-on-chip (SoC) products. The proposed method characterizes PLL loop parameters to increase test quality with minimum additional test time and 4.5% accuracy in IBM 65 nm technology. A self-correction mechanism accompanies the proposed BIST to recover performance variations resulting from excessive process variation found in high-volume manufacturing (HVM). The proposed IDDQ BIST circuit's performance is evaluated in silicon using 0.18μm technology and achieves 2% accuracy with only 1.7% additional PLL area overhead. Extensions to other analog mixed signal circuit blocks should be possible.
Analog/Mixed-Signal (AMS) Power Systems-on-chip (SOC) require variety of current-based tests to be performed, with large dynamic range: from leakages in micro-ampere levels to high power load regulations and current limit test in multi-ampere levels. Limitations associated with automatic test equipment (ATE) incur high test cost in the form long test times and additional hardware required to multiplex high power resources to device-under-test pins. In our work we propose a framework for forcing and measuring currents on-chip via combo-DFT (built-in current sensor, current DAC, recycling and ATE co-test methodologies) and achieves >;50% reduction in manufacturing test time and 50% reduction in ATE resource requirements.
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